1. Field of the Invention
The present invention relates to a data processing system and a data processing method.
2. Description of the Related Art
An example data processing system is an image data processing system including a plurality of image data processing sections which are combined so as to conduct a series of data processing.
Such an image data processing system is, for example, employed in a digital still camera or the like, in which a plurality of image data processing sections are combined so as to conduct a series of data processing. In a digital still camera, after image data is taken by a CCD module, the camera needs to perform: color density conversion, such as color space conversion of the RGB values (color signals) of a Bayer""s array to YUV values (brightness signals and color difference signals), auto iris (adjustment of an output value depending on light and shade), and white balance (color adjustment); compression of an image into a JPEG format; and the like. If such image data processing is sequentially executed, the processing time is simply accumulated and the overall processing time is considerably long. In this case, for a digital still camera or the like, a quick response is impaired for taking an image. An example image data processing system will be described below with reference to FIG. 8.
FIG. 8 is a block diagram illustrating a structure of a conventional image data processing system. In FIG. 8, an image data processing system 800 includes: a plurality of image data processing modules A through C; a memory controller 103 which accesses an external memory 102 (data write and read); a single bus 101 shared by the image data processing modules A through C, which connects the image data processing modules A through C and the memory controller 103; and a DMA (Direct Memory Access) controller 104 which controls the image data processing modules A through C and the memory controller 103. The image data processing modules A through C each generally perform different image data processing for input data. Note that the image data processing modules are examples of a data processing module.
The image data processing module A processes image data received from an input section 105. A result of the data processing (referred to as data A) is output via the bus 101 to the memory controller 103. Data A is written by the memory controller 103 into the memory 102 at an address which is output from the DMA controller 104.
Thereafter, data A is readout from the memory 102 by the memory controller 103, and read data A is then input via the bus 101 to the image data processing module B. The image data processing module B processes the received data A. Thereafter, a result of the data processing (referred to as data B) is output via the bus 101 to the memory controller 103. Data B is written by the memory controller 103 into the memory 102 at another address which is output from the DMA controller 104.
Thereafter, data B read out from the memory 102 by the memory controller 103 is input via the bus 101 to the image data processing module C which in turn processes data B. Thereafter, a result of the data processing (referred to as data C) is output to the output section 106.
As described above, when the image data processing modules A through C perform data processing in sequence, the overall data processing time is a sum of each image data processing time. Thus, it takes a long time to perform the entire image data processing. In this case, for a digital still camera or the like, a quick response is impaired for taking an image.
Japanese Laid-Open Publication No. 5-48911 discloses a method for solving such a problem, for example.
FIG. 9 is a schematic block diagram illustrating an image data processing system 900 in which data processing is sped up by adopting conventional pipeline processing.
The pipeline processing is a method in which one process is divided into n separate processing steps which are arranged on a line, and the processing steps are conducted in parallel. In the pipeline processing, a series of data processing results are successively obtained every one nth of a time required for processing the entire processing.
In FIG. 9, the image data processing system 900 includes: an image data processing module D which processes image data received from an input section 901; a temporary retaining memory 902 which temporarily stores a result of the data processing by the image data processing module D; an image data processing module E which processes the data processing result stored in the temporary retaining memory 902; a temporary retaining memory 903 which temporarily stores a result of the data processing by the image data processing module E; an image data processing module F which processes the data processing result stored in the temporary retaining memory 903; an output section 904 which outputs the data processing result by the image data processing module F. These sections, modules and memories are arranged in the form of a pipeline in terms of time and address space. In the image data processing system 900, a subsequent stage starts data processing partway through data processing in a previous stage (the previous stage means one of the image data processing modules which is positioned at the input side before the subsequent stage, and the subsequent stage means one of the image data processing modules which is positioned at the output side after the previous stage). Therefore, such parallel data processing leads to a reduction in the overall data processing time.
In xe2x80x9can image reading apparatus and a digital copying apparatusxe2x80x9d disclosed in Japanese Laid-Open Publication No. 5-48911, data processing modules are arranged in the form of a pipeline so as to speed up the digital data processing of the copying apparatus. In Japanese Laid-Open Publication No. 5-48911, a document reader (corresponding to the image data processing module D) reads a document, partway through which an encoder (corresponding to the image data processing module E) starts encoding, and subsequently a decoder (corresponding to the image data processing module F) starts decoding partway through the encoding process by the encoder. Thus, a plurality of image data processes are conducted in parallel for a certain period of time, thereby reducing the overall processing time for an entire image data.
More specifically, in the image reading apparatus and the digital copying apparatus disclosed in Japanese Laid-Open Publication No. 5-48911, two memories (corresponding to the temporary retaining memory 902 shown in FIG. 9) each capable of storing data of the number of horizontal pixels multiplied by 8 lines are provided between the document reader and the encoder. The encoder requires data of 8xc3x978 pixels for a unit process. The encoder starts encoding when data of 8 lines are stored after the start of outputting of the document reader. Similarly, the decoder also starts decoding partway through the encoding process of the encoder. Thus, the reading, encoding, decoding, and outputting processes are executed in parallel at the same rate, thereby reducing the overall processing time for an entire image data.
However, the pipeline processing as described in Japanese Laid-Open Publication No. 5-48911 cannot be applied to the CCD data processing (reading, encoding, decoding and outputting) of the above-described digital still camera. In CCD data processing, a previous image data processing module cannot wait image data processing, and a subsequent image data processing module cannot delay image data processing if the temporary retaining memory 902 or 903 is likely to overflow.
Further, if a subsequent image data processing module processes image data faster than a previous image data processing module does, the subsequent image data processing module adversely overtakes the previous image data processing module. In this case, the above-described pipeline processing is impossible.
Therefore, when a plurality of data processing modules have different data processing rates, the above-described pipeline processing is impossible. The overall processing time for an entire image data cannot be reduced.
According to one aspect of the present invention, a data processing system comprises: a plurality of data processing modules for performing a series of data processing, wherein each of the plurality of data processing modules processes data; a bus connected to each of the plurality of data processing modules; a memory controller for writing the data processed by each of the plurality of data processing modules into a memory via the bus, and for reading out the written data from the memory via the bus; a DMA controller for determining operation of each of the plurality of data processing modules, and outputting an address to the memory controller, the data processed by said data processing module being written at the address and the DMA controller including a data parallel processing control section. The plurality of data processing modules includes first and second data processing modules, and the second data processing module is subsequent to the first data processing module in the series of processing. The DMA controller has a coordinate counter for managing the address, and according to a value of the coordinate counter, the DMA controller controls the first and second data processing modules so that the second data processing module starts data processing before the first data processing module completes data processing.
When a bus is sufficiently fast for each data processing, data input and data output of a previous data processing module are intermittent, so that a DMA controller allows another data processing module to receive or output data. Therefore, even when each data processing module has a different rate, a previous data processing module and a subsequent data processing module can be conducted in parallel, and the overall processing time required for an entire image data processing can be reduced.
In one embodiment of this invention, the data parallel processing control section includes a no-overtake control section, wherein when the second data processing module has a faster processing rate than that of the first data processing module, no pass control is applied to the second data processing module so that the second data processing module is prevented from overtaking the first data processing module in terms of the data processed.
Even when the data processing rate of a subsequent data processing module is faster than the data processing rate of a previous data processing module, the subsequent data processing module can be prevented from overtaking the previous data processing module. Therefore, data processing can be satisfactorily conducted in the previous and subsequent data processing modules.
In one embodiment of thin invention, the no-overtake control section ends operation of the no-overtake control after the first data processing module completes data processing.
If a difference between each count value is continuously controlled so as not to be less than or equal to a given value after a previous data processing module has completed its task, a subsequent data processing module cannot complete its task. To avoid this, no-overtake control is disabled so that final data can be subjected to data processing.
In one embodiment of this invention, in the series of data processing, a plurality of processing lines branch from a single processing line.
In one embodiment of this invention, in the series of data processing, a plurality of processing lines are merged into a single processing line.
Data processing may not be a single line. For example, input data from a CCD or the like may be divided into a brightness component and a color component which are subjected to different processing. In other words, a certain image data processing module may have a plurality of outputs, or conversely, a plurality of inputs and a single output. Even in such a case, data processing can be sped up. Even when data processing is not always sequential and includes processing branches, the data processing can be sped up.
In one embodiment of this invention, the data processed in the series of data processing is image data.
The data processing system of the present invention can be easily and satisfactorily applied to an image data processing system. Especially in the case of image data, since image data has a great amount of data compared with typical data, a reduction in processing time is significant in the present invention.
According to another aspect of the present invention, a data processing method for use in a data processing system including a plurality of data processing modules each connected to a bus, and a DMA controller for controlling each of the plurality of data processing modules, the plurality of data processing modules including first and second data processing modules, comprises the steps of: a) processing data using the first data processing module; and b) processing the data processed by the first data processing module, using the second data processing module before the first data processing module completes data processing. The DMA controller controls the second data processing module so that in step b, the second data processing module is prevented from overtaking the first data processing module in terms of the data processed.
Thus, the invention described herein makes possible the advantages of providing a data processing system and a data processing method which can reduce the overall processing time even when a plurality of data processing sections each have a different data processing rate.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.